Monday, August 18, 2014

CAN bus communication hardware schematic diagram (using TJA1050T CAN bus driver


CAN bus communication hardware schematic diagram (using TJA1050T CAN bus driver)
F040 built-in CAN bus protocol controller, as long as the external bus driver chips and appropriate anti-jamming circuit can easily build a CAN bus intelligent control node. This design uses PHILIP company TJA1050T CAN bus driver.
CAN bus communication hardware schematic diagram shown in Figure 3.

F040 figure of CAN signal reception pin RX and TX pins are not sent directly connected to TJA1050T RXD and TXD end, but through the high-speed optocoupler connection 6N137, that the purpose is to achieve electrical CAN bus each node isolation. In order to achieve complete electrical isolation in the true sense, the optocoupler section VA and VB must be isolated by the DC-DC switching power supply module or modules with multiple isolated outputs. To prevent over-current shock, TJA1050T the CANH and CANL pins each connected to the bus via a resistor of a 5Ω. And between CANH and CANL feet and capacitors in parallel two 30P for the bus frequency interference filter. The lightning D1 and D2 may play a protective role in the occurrence of transient interference.
TJA1050T F040 8-pin connector to a port for mode selection, TJA1050T There are two operating modes for selection, high-speed mode and silent mode. TJA1050T to work in high-speed mode, and in silent mode, TJA1050T the transmitter is disabled, perform listen function can be used to prevent the network due to the CAN controller out of control and cause obstruction.

SC-232/485 interface circuit

SC-232/485 interface circuit

FSK modulation and power line interface circuit

FSK modulation and power line interface circuit

High output level RF modulator circuit

High output level RF modulator circuit

USB signal generating circuit diagram


USB signal generating circuit diagram

48V DC input 12V output step-down circuit

nput 12V output step-down circuit

Minimum System Diagram

Minimum system (power supply circuit and I / O expansion and gating circuit) 

  design uses minimal system board is based on 80C52 microcontroller as the core, and has good scalability. CPU external crystal 11.0592MHz, mainly by 74LS373 latch circuit, 74LS138 decoder circuit and keys, display devices, ICL7135 its peripheral typical circuit, with 8255 foreign expansion of I / O interfaces. Minimum system circuit shown in Figure 2.
2 minimum system schematic diagram
  This circuit requires external transformer an AC220 / 9V, the secondary side of the transformer is rectified and filtered through CW7805 can get + 5V input voltage, this voltage power supply to do the smallest system.
  System by 8255 to expand outside the PA, PB, PC total 24 I / O ports, so that as the system's input and output channels. 74LS138 output as decoded by the selection terminal of each chip, in addition to the minimum outer Y0 ~ Y3 used in the system, as well as Y4 ~ Y7 available to other extensions.